Based on DSP and the OV6630 image sensor acquisition system (1).

<P> Introduction </ P> <P> DSP is based on the programmable ultra-large scale integrated circuit and computer technology developed an important technology, DSP chips, fast data acquisition and processing capabilities, and features integrated on-chip DSP module .used in various occasions, provide a great convenience. .The CMOS image sensor and CCD compared to the CMOS image sensors, timing can image signal processing circuit and the digital part of the front-end amplification and integration in a chip, so its development has been the industry's attention. .Now, with technology and process development, CMOS image sensors have been not only improve on the noise, and the resolution has also been significantly improved. .CMOS image sensor with its low price and practical image quality, high integration and power consumption of a relatively small area in the video capture is widely used. .Therefore, this paper presents a CMOS image sensor based on DSP and also by the complex programmable logic control chip CPLD control real-time image acquisition system program. .</ P> <P> 1 hardware design </ P> <P> Figure 1 shows the image acquisition system block diagram of the circuit. .Figure 1 shows the image acquisition system is composed of OV6630 image sensor chip, CPLD control module, SRAM data memory, FLASH program memory, DSP signal processors, composed of several parts. .The image capture chip, developed by the United States Omni Vision CMOS image sensor color OV6630, the chip compared with the conventional CCD sensors, the most obvious advantage is that high integration, low power consumption, low production costs, easy integration with other chips .. .The CMOS light sensor chip will support the core and peripheral integrated circuits. .Because of its use of a proprietary sensor technology, which can eliminate the common optical interference. .The chip's pixel array is 352 × 288, or 101,376 pixels, and 4 rows, 4 columns to choose from. .The output of image data in various formats (YCrCb4: 2:2, GRB4: 2:2 and RGB raw data output format), the system selected 8-channel output Y output RGB raw data formats, and progressive scan work. .The output format is: </ P> <P> odd lines BGBG ... ... </ P> <P> even lines GRGR ... ... </ P> <P style = "TEXT-ALIGN: center" done5 = "3 ."> </ P> <P> According to the human eye is not high on the color response bandwidth characteristics of a large area of color, while the output of each pixel is not necessary in 3 colors. .Therefore, the data sampling, the odd scan lines 1,2,3,4, ... pixels were sampled and the output B, G, B, G, ... data; even lines 1,2,3,4, .... pixel sampling and output, respectively, G, R, G, R, ... data. .In actual processing, each pixel of the R, G, B signals output by the pixel itself, a color signal and an adjacent pixel color signal output form the other. .This sampling method does not reduce the image quality in the basic, while the sampling frequency can be reduced by 60% or more. .</ P> <P> system core processing chips used TI's fixed-point DSP chip enhanced TMS320VC5410A, the DSP's operating frequency of up to 160 MHz, internal 64KBRAM room for flexible map data or program memory space. .The DSP's internal memory space is limited, therefore, the design of the external expansion of a size 1 MB of SRAM data memory and 256 K CY7C1021 the FLASH program memory SST39VF400A. .Control chip used Altera's MAX7000 CPLD chips EPM7128SLC84-15. .The chip contains 84 I / O pins, 128 macrocells, each macrocell 16 can form a logic array block, the working voltage is 5.0 V. .The chip in the system timing control in the overall position of both the image sensor chip used to provide control signals. .SRAM and FLASH is also used in the chip select and write control, LCD display is also responsible for control. .</ P> <P> 2 software design </ P> <P> when the system configuration is finished, it can be image data acquisition and processing. .Images in the collection process, the most important task is to determine a beginning and end of image data of the moment. .After careful consideration of the OV6630 output sync signal (VSYNC vertical sync signal, HREF is the horizontal sync signal, PCLK is the output data synchronization signal) basis. .I realized with VHDL, the starting point of the precise control of the acquisition process. .Figure 2 shows the three synchronization signal during image acquisition and data signal timing diagram. .</ P> <P>.