The rapid development of computer technology, embedded image system widely used Office equipment, manufacturing and process design, medical, surveillance, sanitation, transportation, communications, finance, banking system and a variety of information appliances.
The so-called embedded image system, refers to the image as a Center for computer technology, software, hardware, you can reduce the functionality, reliability, cost, size, power consumption, the strict requirements of special-purpose computer systems. Embedded image system for image display technology offers a variety of strictly required, you must select the appropriate display, design a reasonable display control method.
System hardware design
System to build an embedded, high speed, low power, low-cost image display hardware platform requirements can true color display static or dynamic color images.
In order to achieve true color and no trailing display dynamic images, both the low power requirements, the use of SHARP (sharp) company LQ057Q3DC02 color TFT-LCD as monitor; in order to achieve the real-time image processing and display, using Texas instruments (TI) company high-performance DSP TMS320C6711 as the primary processor; DSP and data interface between TFT-LCD and driver control by TFT-LCD CPLD ispMACH4064V and high-speed bulk FIFO AL422B completed. System hardware diagram shown in Figure 1.
Figure 1 system hardware diagram
1, TFT-LCD drive control hardware design
1 and 2, CPLD driven control to display an image, to TFT-LCD produce three clock signal: data transfer clock (CLK), line synchronization clock (Hsync) and frame synchronization clock (Vsync), and through the 18-bit parallel data bus (R0 G0 ~ ~ R5, G5, B0 ~ B5), and the clock signal to synchronize write image data to be displayed (D0 ~ D17).
Figure 2 LQ057Q3DC02 internal chart
LD driver control TFT-LCD hardware circuit shown in Figure 3.
2. storage design
Minimal use of CPU resources, so that the CPU has more time for image acquisition and processing, and output image in the CPU to process monitor TFT-LCD intermediate storage for data buffer.
Regular high-speed CPU data is output to the cache, and display platform then according to the driving time readout TFT-LCD data for display. CPU output data rate is greater than the read speed display platform, the cache is a high speed write, slow readout process. CPU to 40ms for cycle regular output data, and display platform is continuing to read out the data to display, cache write and read out process is complicated.
Figure 3 CPLD driven control TFT-LCD hardware circuit diagrams
The system adopts AVERLOGIC company based on DRAM bulk FIFO AL422B as the buffer cache.
3.3V AL422B working voltage, can withstand a 5V, maximum access speed, capacity 384Kb 50MHz, system image to be displayed with each frame, so AL422B 225Kb may very well meet the high-speed, high-capacity and low-cost system requirements. AL422B no empty, half full and full, state flags, the weaknesses of the system hardware design and control of a certain degree of difficulty.
422B is synchronous FIFO, reading clock (RCK) and write clock (WCK) two clock signal.
AL422B adopts DRAM for storage media, you need to regularly refresh on-chip data. Chip auto-select frequency higher clock signal as DRAM refresh clock, the device work with at least one clock signal frequency cannot be lower than 1MHz. AL422B of functional block diagram shown in Figure 4.
Figure 4 AL422B functional block diagram
3 DSP interface design
Digital image processing refers to the given time interval for external input of digital image processing to complete the specified input into the image processing is complete output delay than image data update rate.
If each frame to a 320 × 240 × 18-bit, 25f/s image signal, its data rate 5.5Mb/s, for real-time processing, the processor must be greater than the rate on 5.5Mb/s, i.e. the system in a finish to 40ms frame images of all operations, including image acquisition, storage, transmission, processing and display. Image acquisition rate by CCD image sensor for example, the image data storage, transmission, processing and display are depends on CPU performance. General device does not meet the system requirements in real time, so the system uses TI (United States Texas instruments) company high-performance universal DSPTMS320C6711 as the system's main CPU.
System, use the EMIF TMS320C6711 of 8-bit asynchronous way time with CPLD with refreshing external synchronization FIFOAL422B, interface circuit as shown in Figure 5.
Figure 5 TMS320C6711 and FIFOAL422B interface circuit
Provide for AL422B P6711 write reset signal (/WRST) and write-enable signal (/WE).
CPLD based DSP6711 provides out-of-core enable signal (/CE) and write enableCan signal (/AWE), to provide written synchronous clock AL422B (WCK). DSP6711 through data bus ED [5: 0] image data is written to the internal storage unit AL422B.
4, CPLD design
This system uses ispMACH4064V (4064V) as the display platform master logic devices.
4064V is a work in the vicinity of CPLD glow new chips, I/O port compatible with 5V TTL level, main performance parameter as shown in table 1.
IspMACH4064V is TFT-LCD, FIFO and DSP EMIF mouth three devices logic function time series of core components, in order to achieve the timing between strict synchronization, using an external clock reference source input to the internal ispMACH4064V, ispMACH4064V are all signals to the clock basis.
System total
TFT-LCD color digital image display platform of three key components, namely the DSP, FIFO and CPLD.
DSP will periodically through the EMIF mouth image data to the FIFO; continuous read CPLD parallel FIFO in image data driven TFT-LCD display dynamic or static color digital images. DSP write FIFO speeds up 25MHz, TFT-LCD refresh clock 6MHz, CPLD read FIFO speed should be greater than 3 times the TFT-LCD refresh clock, 24MHz. Timing between various devices must match exactly, in order to properly display the image. This system uses CPLD ispMACH4064V Lattice, the company produces TFT-LCD driver timing and FIFO reading time series, together with the DSP EMIF mouth write sequential formation of FIFO. System design is a digital image display technology is the key point, is also the most difficult part.
System power-on reset after CPLD, FIFO and TFT-LCD, DSP scheduled to FIFO writing image data, CPLD parallel read FIFO, while driving TFT-LCD-by-pixel image, the system always process as shown in Figure 6.
Figure 6 system flowchart
This system uses the VHDL language on the CPLD functionality you want to achieve behavior descriptions Synthesis software on VHDL source code syntax checking and logic synthesis, ispLEVER3.0 environment to conduct functional simulation, ispMACH4064V temporal simulation, pin I/O settings and assignments, and finally the JEDEC file will be generated with a download cable writes CPLD, generate actual digital logic.
Based on image processing system performance analysis
Image processing is finished, you will need to show to the people make observation and assessment.
Human visual system is very sensitive to color, image display of color must meet or exceed the person's ability to distinguish, they will not lose useful image information. Image processing system for image display must achieve true color (18-bit color) display. For the embedded digital image processing system for real-time performance requirements, image display module to do less DSP resources while true color display means that greater data throughput, these require image display module to have faster processing speed.
This system, a frame image is a total of 320 × 240 × 3 = 225Kb, DSP using 8-bit asynchronous mode to 25Mb/s rate to FIFOAL422B write image data, write a frame image desired 9ms.
If DSP to 40ms intervals refresh AL422B image data, you can achieve smooth animated colour digital image. Such data throughput speed is a good way to meet real-time performance requirements.
And market similar products: domestic and foreign markets, control color TFT-LCD generally use ARM, MCU with TFT-LCD interface, or directly using a dedicated IC, or even use the IPC, which are difficult to meet the cost of embedded systems and power requirements.
The domestic market, a few companies with programmable devices + storage technology develops practical products, most of the image using SRAM as data memory. Because of the need to carry out complex read-write port switch, these products generally use high-end programmable devices while reducing image display quality, not true color display, unable to display dynamic image smoothly. While this topic implements the 18-bit true color display, 25 frames per second, dynamic image display can be smoothly and cost only 40 RMB, greatly improving the product price.
Conclusion
This article presents an approach based on DSP colour digital image display solutions TFT-LCD, using high-performance DSP, and based on the new large-capacity DRAM FIFO memory that has driven CPLD TFT-LCD and DSP data interface of all time.
And compared to similar products on the market, this system dramatically improves image quality and display speed, lower power consumption and system cost, in the embedded image system has broad application prospects.
