Based on the CPLD programmable broadband high precision CCD signal generator design (1)

1 Introduction

CCD (Charge Coupled Devices) charge ouheqi piece is in the early 1970s, developed new semiconductor devices.

Currently CCD as sensor photoelectric because it has small size, light weight, small power consumption, low operating voltage and resistance to fire, and other advantages as well as in the resolution, dynamic range and sensitivity, real-time transmission, since the scan features, widely used in photography materials, meteorology, aerospace, military, medical and industrial testing.

We need to get to the CCD camera is a high speed image data acquisition, storage, and for subsequent processing and application, but for this series of signal processing before the target signal acquisition and the quality of the signal to debug the entire camera system.

When debugging a camera system, since the debugging system always has some imperfect factor, but also because many debugging also increases the risk of the CCD chip costs, especially for more expensive CCD chip, debugging if you often use will lead to the risk of damage, so debugging on the CCD chip output signal analysis simulation and became an extremely important work. This article has designed a method based on CPLD programmable broadband, high-precision CCD signal generator. Take full advantage of CPLD programmability, emulate the CCD in the complex environment of acquisition signals, at the same time meet the system requirements of the waveform and timing, the output signal frequency reaches 11MHz.

2 analysis of the characteristics of the CCD output signal

A CCD signal output sequence is a reset pulse start, when the FET switch is shown in Figure 1, the voltage of the capacitor on the sensor as the initial value of the reference voltage, this reference voltage value is called reset feed through level.

After a certain amount of feed through the delay time, the voltage value reduced to become real reduction level. At this point, the FET switches to open, the pixel charge was transferred to the capacitance, the corresponding change in the capacitor voltage value on. The voltage value is the reference level, pixel-level as well as some noise superimposed. When you start work read valid CCD signal, the output signal at each reset signal of the rising edge, i.e. when the reduction in output signal interference pulses on the reset, and then back to reference 1 level 2, start by reading the integral is pixel signal 3. Actual pixel width is the width of 3, 1, 2, 3, width and is one pixel cycle, each pixel of the signal amplitude is 2 and 3 of the height difference, the CCD output signal of the important parameters. CCD output signal contains large DC component. DC bias voltage is a CCD to function is missing, the value of a few volts to range dozen volts, and only consume a few Ma following current, easily by regulated power supply necessary with resistance or potentiometer divider and capacitor filter.

Figure 1 CCD output signal

3 hardware structure

The entire system consists of a digital signal generator modules, digital-to-analog conversion module and output processing module 3-part.

Select the CPLD to form a signal generator modules, making full use of its programmability, constructed out of the CCD in the complex environment of collecting data while generating and data signal that matches the control signal, control of subordinate work of DAC module. To-analog conversion modules receive superior sent data and control signals, control signal control data to be converted to analog signal output. Due to the transformation output module for current, so you also need to add a translation module converts the current system voltage signal, at the same time in order to satisfy the system requirements on the precision of the signal, also need to increase the active and passive filter circuits module. System block diagram shown in Figure 2, crystal oscillator as a CPLD clock (clk) signal input, the other by its result.

Figure 2 system block diagram

The main work is divided into the following areas:

(1) a signal generator module

Use of VHDL Design CCD output image signals and timing control signal, the output signal is simulated digital image signals (10-bit parallel output) and timing control signal, mainly including: correlated double sampler, A/D sampling the desired timing pulse signals, row, field synchronization pulse signals, etc.

(2) digital-to-analog conversion module

The simulation of a digital signal via

-Analog converter receive analog signals, high speed DAC parts usually current check output, so you need to output analog signal for subsequent processing.

(3) output processing module

On DAC output from the analog signal, through operational amplifiers convert voltage output signal, and further processing be consistent with the requirements of the CCD output signal.

4 signal generation module CPLD design

4.1 select compliant CPLD

This design uses LATTICE company ispLSI1032e CPLD, the chip has a total of 84 pins, the number of available door up to 6000, 192 logical unit, can be individually configured for input, output, and bidirectional working mode, 64 common i/o port, its propagation delay for 7.5ns, maximum operating rate 125MHz, can meet the design requirements.

The system requirements of the output frequency is 11MHz of double sampling forms of CCD signal and the signal timing has strict requirements, selection of crystal oscillator, as 66MHz CPLD clock input.

4.2 program design

The output of the digital signal to provide to the image sensor of the next-level sampling system, to meet certain timing requirements, sampling the timing pulse signal, the output signal is analog CCD output signal, double sampling signal, so you need A/D introduce synchronization pulse signals, etc.

Signal generation module CPLD part, we need to have all of the digital signal, you need to for the next part of the ready-to-analog conversion module requires data and D/A clock timing.

In the use of VHDL language in an ISP environment programming, simulation, testing, get a few simulation grayscale images and lines, field synchronization signal.

Output signal is digital image signals (10-bit parallel output), D/A clock signal (clock1) and write signal (wrt), double sampling signal, row, field synchronization pulse signals, etc. Input clock (clk) 66MHz, line synchronization signals row used to ensure the synchronization of the output pixel.

Its output as an analog CCD data generation and D/A conversion control module of the clock input.

Analogue CCD data generation module output of square wave signal ccdout [9 ..0], after the DAC transform, build CCD analog output signal. D/A conversion control module generates the Write DAC signal WR and clock signal CLK, D/A in data ccdout [9: 0] of a cycle of high and low level the sampling conversion once need wrt and clock1 in ccdout [9 ..0] of high and low level respectively sampling, in order to guarantee the clock1 and wrt signal phase relationship, wrt signal rising edge of the clk, the signal at clk clock1 drop along the transform, which produces we need data and control signals.

4.3 simulation results

This design enables use of VHDL language and hardware programming CPLD generates system data source signals, including simulation of the CCD output analog signal generation ago set digital signal and for the next level of control required for timing, ensures that the system output signal and phase relation of speed.

As in Figure 3 as shown in the simulation waveform, ccdout [9 ..0] image for analog signals, shp, shd be correlated double sampler, clock1, wrt to the next level-to-analog conversion module D/A control signal. Reference pulse pulse shd shp and video in a pixel interval respectively sampling time, final output signals for acquisition to the reference level and the difference between the video level, using correlated double sampler you can filter out the overlay in the output signal on the reduction of noise.