Based on the logic of the kernel's FPGA circuit debugging techniques

With the FPGA into more and more capacity to effectively debug tool needs will become crucial. On internal Visual ability prior careful planning will enable development teams to adopt the correct debug strategies to faster completion of their design tasks.

"I know my design has a problem, but I didn't need to quickly find problems of internal Visual capabilities.

"Because of the lack of adequate internal Visual capabilities, debugging FPGA-based system may be frustrated. Use usually contains the entire system of large FPGA, debugging the Visual ability to become a big problem. The ability to access internal Visual, design engineers must put some pins designed for debug pins, rather than the actual design. What tools can be used for measuring internal FPGA trace? and what technology available fixed pin count maximize internal Visual ability?

FPGA design engineers have two internal trace measurement methods:

1. put node routing to pin, use the traditional external Logic Analyzer.

2. make a Logic Analyzer kernel into FPGA design, FPGA by internal JTAG memory saved trace captures routing output.

Logic analysis

FPGA developer to make important early in the design of the judgment, they consciously or unconsciously determine how to debug their designs.

Get the internal FPGA Visual capabilities of most commonly used method is to use Logic Analyzer, interesting interior node route-analysis meter detection PIN. This approach provides deep memory trace, where problems of formation and its influence may have a great time interval. Logic Analyzer can measure may escape simulation of asynchronous events. One example is a non-relative frequency of two or more clock domain interaction. Logic Analyzer provides powerful triggering the measurement results can be established with other system events time-related.

Conventional logic analyzers provide status and timed mode, it can be either synchronous or asynchronous to capture data.

In the timed mode, design engineers can see signal transitions. The State pattern, design engineers have the ability to observe the relative to the State of the clock of the bus. When debugging bus values crucial data path, the state mode is particularly useful.

Effective real-world measurements need careful planning.

The use of conventional logic analyzers to take account of the principal balance is the node routing output to detectable in PIN. Traditional Logic Analyzer can only be observed the signal routing to pin. As also do not know the potential of in-circuit debugging problems, design engineers can only put a few pins used for debugging. This way less PIN number may be insufficient to provide adequate solutions to the issues at hand, the Visual ability to delays in project completion.

Maintain internal Visual capabilities, while reducing the number of dedicated to debug pin of one method is to insert in the design of the switch multiple converters (see Figure 1).

For example when the FPGA design into the circuit, you may need to observe 128 internal node, this requires a trace of 32 channels. In this case, you can implement in FPGA design multiple converters in a given time routing out of 32 nodes. For programming multiple converters, design engineers can download a new configuration file, using the JTAG or through multiple converters on the line of control signal via the routing switch. In the design phase, you must carefully test insert multiple converters. Otherwise, the design engineer may stop to simultaneously access a node needs to be debugged.

Figure 1: test insert multiple converters enable design engineers have the ability to route out the internal subset of the signal, the figure for the Agilent 16702B captured trace.

Minimize the number of debugging dedicated pin of the second method is time division multiplexing (TDM).

TDM multiplexing is commonly used to design prototypes, then put the multiple pieces FPGA chip ASIC prototypes as, so to minimize the number of special pins for debugging. This technique is best suited to handle a slow internal circuits. Assuming that use 8-bit bus 50MHz design (clock along for 20ns) need Visual ability within the circuit. Use 100MHz during the first sampling low 4bit 10ns, in the second period of sampling high 10ns 4 bits. This is used only to 4 pin, you can each 20ns cycle captured all the 8-bit debugging information. After the capture of trace, combination of successive 4-bit capture the trace of the reconstruction of 8 bits. TDM multiplexing also has some disadvantages. If you use the traditional Logic Analyzer to capture trace, trigger becomes very complicated and prone to error. For example, in 8-bit code for the type of trigger to include the logic analyzer set to look for the following provisions of the code type 4 digits after another specific 4-bit formats. But Logic Analyzer does not know which a 4-bit is an 8-bit groups, so you want to trigger settings that match the conditions that trigger-instead of using the trigger conditions and Italy.

When using TDM multiplexing gain measurements are accurate periodic.

But the design engineer lost clock timing relations during the week. Usually single pin speed and Logic Analyzer collects trace of acquisition speed (state mode) limits the compression ratio. For example, if the maximum speed is a single PIN, internal circuit 200MHz runs at up to 100 MHz, the achievable maximum compression ratio is 2: 1.

With the maturity of the given FPGA design, it can be enhanced and change.

Originally designed for debugging PIN will be used to design enhancements. Or start limits the design of the PIN. Another debug technology to bring value to such situations.

Kernel-logic analysis

Now most FPGA manufacturers also provide logical analysis (see Figure 2).

These IP in synthetic insert before or after the FPGA synthesis. The kernel contains the trigger circuit, and is used to set measurement and internal RAM to keep track of resources. Into the design of logical analysis of kernel changes the design of the timer, so mostDesign engineers have the kernel permanently stay in design.

Figure 2: from JTAG download Logic Analyzer configuration diagram example is Xilinx ChipScopePro.

For in-circuit emulator, which could access the kernel via JTAG, as well as observation and capture data transfer to PC.

If the kernel is not consumed to 5% of the available resources, FPGA core can give full play to the role. If the dimensions of the FPGA allows the kernel to consume more than 10% of the resources, the design engineer with this approach will encounter many problems.

Logical analysis of the kernel has three major advantages.

1. their use does not increase the PIN.

Available through the FPGA on specialized JTAG pin access. Even if there are no other available pins, this debugging method also get internal Visual capabilities.

2. simple detection.

Detection include node routing internal logic analyzer input. Do not need to worry about to get valid information, how to connect to a circuit board, nor the signal integrity problems.

3. the logic of the kernel is cheap.

FPGA manufacturers put their business model to use silicon wafers acquired on the basis of the value. So the debugging IP usually at less than $ 1,000 price.

Use the internal logic of the kernel also has three areas of influence.

1. kernel size limits on the use of large FPGA.

In addition due to internal FPGA storage is used to track, trace depth is very brief.

2. design engineers must abandon the internal memory is used for debugging, memory will be used for the design.

3. internal logic analyzer only works in state mode.

They captured data and provides time synchronization, but can not provide signal timing relationship.

Hybrid technology

Some FPGA manufacturers have started with the traditional Logic Analyzer manufacturers jointly developed combination technology (see Figure 3).

For example, Agilent and Xilinx recent joint development for Xilinx of ChipScope 2M State deep memory.

Figure 3: mixing inner and traditional logical analysis of the first example is the joint for Agilent and Xilinx ChipScopePro developed deep memory, by TDM multiplexing can pin count to a minimum.

The solution to the internal logic of the kernel used to trigger.

In the trigger conditions meet the kernel, the kernel to trace information from the routing node passed to the kernel, and then sent to the PIN. PIN mictor connector through a small external track boxes. The solution incorporates TDM multiplexing to reduce debugging dedicated pin count. According to the internal circuit speed, multiplexing compression may be 1: 1, 2: 1 or 4: 1. Because the track is not saved in internal, so IP cores to less than with trace IP storage logical analysis.

How to make a decision?

Traditional logical analysis and the analysis based on kernel-logic technology are useful.

In choosing the most suitable for your debugging needs, prior to consider some factors will be able to assist you in making a decision. The following questions can help you decide which programmes are most effective.

1. you are expected to encounter which type of debugging problems? use internal logic Analyzer cannot find a simple question, but the traditional Logic Analyzer is capable of performing complex failure.

2. in addition to state mode, you need to capture the timing information? if required, the traditional Logic Analyzer can meet this requirement.

3. need more deep trace of? traditional Logic Analyzer to capture in all channels up to the track, 64M while the internal logic of the kernel more suitable for discussion of the track.

4. how many pins can be dedicated to debug?, the less pin count, use internal logic Analyzer will be suitable.

5. must be a new tool into money? although 32 channel traditional Logic Analyzer starting at $ 6K, but internal logic Analyzer and accompanies Waveform Viewer starting at less than $ 1K.

6. the development of the Group intolerable in the impact of FPGA design? kernel can only work on large FPGA and will change the design of the timer.

On all dimensions and types of FPGA, traditional Logic Analyzer routing signal output on design and work with little impact.