HHCE (Home Health Care Engineering) this subject is with human health and the development of telemedicine and gradually go into people's lives.
It advocates a "medical home, self-care, remote diagnostics" concept, the high-tech and health care. The emergence of HHCE meets 21st century society ageing, health care costs rising and the high quality of living healthy demand trends, while achieving medical resource sharing, improving the level of health care in remote areas, it has a special vitality. HHCE system provides a way for families, community health, practitioner of effective and efficient medical monitoring solution with ECG monitoring function of the monitor is an important part of HHCE system. As far as the domestic, these products also belong to the start-up phase, the remote network is just a simple complete database of medical data storage and transmission, there is no truly complete network and medical equipment. At the international level, the world in this study are to invest a great deal, but still mainly use expensive instruments complete medical data collection, and then rely on the PC/internet network through data collection and Network Diagnostics [1].SOPC (Programmable System On Chip) programming system on chip, along with the modern computer-aided design technology, EDA (Electronic Design Automation) technology and LSI technology development arises, is a SOC based on FPGA solutions.
This design uses a technique to Altera SOPC company NiosII soft core processor as the CPU, and transplantation of today's mainstream uclinux OS. The system has high stability, portable, feature upgrade extensions, remote control for users, and so on.1 system introduction ECG monitor portable remote primarily ECG front-end acquisition and conditioning module, ECG signal processing and storage modules, data display module and remote transmission control modules, and so on four key modules, system feature structure as shown in Figure 1.
The monitoring system hardware platforms using Altera CycloneII 2C35 FPGA chip company, SOPC (programmable system on chip) technology will NiosII soft core processor, memory, I/O function interface and extended in a outlet, integrated FPGA chip, peripheral expansion ECG data acquisition board, Internet, LCD screen, touch screen/keyboard, SD memory cards and other hardware to implement system hardware architecture with scalable I/O interface for later system feature upgrades and expansion.
Figure 1 system functional block diagram
2 system design of key modules
2.1 NiosII embedded soft core processor overview
NiosII series embedded processor is Altera Corporation launched the soft core processor.
Users can access more than 200 DMIPS performance, and takes less than 35 cents of FPGA logic resources. NiosII supporting MicroC/OS-II, uClinux and other real-time operating system that supports lightweight TCP/IP protocol stack, allowing users to add custom directives and custom hardware acceleration unit, seamless transfer custom peripherals and interfaces logic, while the increase in performance, convenient design of the user.NiosII processor using Avalon switched bus, the bus is an Altera development a proprietary interconnect technology.
Avalon switched bus from SOPC Builder automatically generated, is a system processor, internal modules and peripherals inline bus between. Avalon switched bus using the least amount of logic resources to support reuse of the data bus, address decoding, wait for the cycle of production, peripheral address, interrupt priority specified as well as advanced switched bus transfer [2].2.2 ECG signal acquisition conditioning module design
The ECG signal acquisition has a modular design, mainly by the front lead sensor, signal filtering Zoom adjustment circuit and A/D sampling circuit.
The main human ECG frequency 0.05 to 100Hz, amplitude of approximately 0 ~ 4mV, signal very weak. At the same time ECG usually mixed in with other bio-electrical signals, coupled with the in vitro to 50Hz-line interference electromagnetic interference, mainly allows ECG noise strong, measurement conditions are relatively complex. Therefore the choice of the rendering device is very important that require device error to very small, and work performance and stability. Considering the design of the ECG signal acquisition conditioning module most components selection Murata Mfg. co., Ltd of electronic components.In order to avoid distortion to detect clinical value of ECG, signal filtering and amplifying conditioning part mainly consists of the following circuit: preamplifier circuit, high and low-pass filter, notch circuit and A/D conversion circuit, circuit schematic diagram shown in Figure 2 as follows:
Figure 2 ECG filtering Zoom adjustment circuit schematics
First ECG collection from weak ECG through preamplifier zoom, this section includes right leg drive to suppress common-mode disturbances, shielded wire drive to eliminate lead and gain set to 10 times.
Design preamplifier mainly uses the United States the simulation component corporate production of medical amplifier AD620 and Murata Mfg. co., resistance and capacitance. AD620 by traditional three operational amplifier developed for phase parallel differential amplifier integration. It has a power range (± 2.3 ~ ± 18V), design of small size, low power consumptionLow (maximum supply current only 1.3mA) characteristics, which make them ideal for low-voltage, low power applications. In addition also has high common-mode rejection ratio, temperature stability, enlarged frequency bandwidth, noise figure small advantages. At the same time it also use Murata seisakusho error range in 0.1% ERJM1 series precision resistance and capacity range in 0.3pF ~ 100uF of GRM series capacitance. Enlarged signal filtering, 50Hz notch treatment after second zoom, after the level gain set to 100 times. Where high (low) pass filtering circuit resistance selection Murata's selection of precision resistor, capacitor capacitance low ESL series, its scope and precision to meet the filter requirements. Notch circuit resistance selection ERJM1 series precision resistor, capacitor uses the LLL series low ESL wide capacitor. Because of the ECG signal amplitude maximum mV on some, and A/D conversion input signal amplitude requires more than the total 1V, gain set to 1000 times. The filter uses the controlled voltage source second order high (low) pass filtering circuit to eliminate 0.05Hz ~ 100Hz bands other than electrical interference signal, the frequency of remaining high harmonics can also be filtered out. At the same time, using Active double-T band-stop filter circuit further inhibit 50Hz frequency interference.A/D sampling chip using TI's 8-bit serial chip, the chip used TLC549 SPI interface, only three lines for acquisition of control and data transfer; 4MHz chip system clock and soft and hardware control circuit, the transformation time of less than 17 μ s, sampling rate up to 40KSPS; the use of differential voltage technology this characteristic, TLC549 may measured minimal values of up to 256, i.e. 1000mv/0-1V signal without amplification can be 8-bit resolution.
2.3 data acquisition controller design
In order to get through the front-end TLC549 chip conversions of ECG, you must design a data controller to AD chips control and acquisition of digital ECG data.
The controller according to the timing of work TLC549 chip [3] and back-end data processing needs, using verilog HDL design itself. The controller has the characteristics of multi-channel acquisition.The i/o from TLC549 CLOCK-enter eight external clock signal period required to complete the following work: read before A/D conversion results; on the conversion of input analog signal sampling and conservation; start the A/D conversion.
The way acquisition time: 0.5us× (3 + 8 × 2 + 1) = 10us, chip switching time is less than the entire procedure 17us time-27us. In order to make effective use of the controller, in the way A/D conversion period, while the other one A/D sampling, so that you can complete the 40us to four signal acquisition, greatly improving efficiency. At the same time, the design also joined a FSM signals to control the sampling time, thus adapting to different frequency signal sampling frequency. The following is a series of AD chip simulation map:Figure 3 simulation time series chart
Din to acquire the data of serial-input, clock from the system clock by frequency coefficient.
Design, set the fsm as sampling control clock so that you can adjust the sampling rate. As a result of an AD sampling time is very short, regardless of the query or interrupt direct read are not realistic, this requires use of cushioning design, through to n times the conversion of data in a temporary buffer memory exists to reduce the interrupts. In order to achieve continuous and accurate data acquisition, seamless buffer, in view of the flexibility of the FPGA design, this design uses a double-buffered storage structure of the table tennis action. This design by AD sampling sequencers alternately stored in two dual-port RAM 512Byte (DPRAM) for data in the cache, if one is stored after DPRAM1 into storage to another DPRAM2 once in and have a break, so that the controller write data to the system will be in DPRAM2 has plenty of time to remove the data from DPRAM1.2.4 display module design
In order to be able to visually display the acquisition of ECG waveform, you need to display device support.
This design uses the LCD Panel is TFT LCD 320 * 240. The LCD module does not display controller, so you need to design display controller IP core to drive the LCD Panel. The design of the display controller IP core using Verilog HDL design, support for multiple color modes, including 18bpp 8bpp, 16bpp, and custom modes. Image memory chip lcd_fifo is FIFO, you can make adjustments as needed. 256-color color lookup tables for on-chip RAM to store. Image information can by Avalon bus master port writes bursty block transfer mode for transmission, use DMA to automatically read from memory, SDRAM image storage image_ram and slice the image data buffer between lcd_fifo has set up a dedicated DMA channel, the controller is structured as follows diagram 4:Figure 4 LCD controller IP core structure diagram
The LCD controller IP core is mainly composed of four modules: interface module, memory modules, color conversion module and timing modules.
Interface module: mainly NiosII processor on LCD controller for control and status reads.
Interface module is the main way to register, which registers are: control register, status register, DMA address register and interrupt register.Memory module: is the primary interface Avalon bus,
After system startup, use the DMA transport mode, through Avalon bus master port writes bursty block transfer mode, the complete image data storage image_ram image data in to slice the image data buffer lcd_fifo independent reading. Using DAM transmission mode is to put the NiosII soft core processor from frequent data read operations work, this can greatly improve the efficiency of the system.Color conversion module: reads the data according to the 4 color mode for the conversion of the data read, 8bpp and custom mode due to insufficient color, you need to access the color lookup table.
Custom models can manually on a palette's address to the preset colors to define output.Timing module: in strict accordance with the sequential write LCD, LCD clock 5M.
By controlling the data enabling signal start lcd_fifo data output progressive scan display. At the same time, the design of the module, in the data valid signal (DE) shall be effective checks before lcd_fifo whether there is data in order to determine whether the data read and transmission; required palette mode settings, in the frame of the transfer process requires a schema lock to avoid transmission errors; under different bpp mode, determine different reading time, every time we read 18bpp, 16bpp interval 1 read, read 4 times 8bpp interval.2.5 data storage module design
This design choice of SD card as external storage hard drive.
SD memory card with a large capacity, high performance, security, and other characteristics of multifunctional storage cards are widely used in digital cameras, PDAs and mobile phones and other portable devices. SD card on all units from the internal clock generator provides clock, interface-driven unit synchronized external clock of dat and CMD signal to the internal clock is used. SD card has two communication protocols, i.e. SD communications protocol and SPI communication protocols, and SPI communication protocol compared to SD communication protocol of the biggest advantages is read/write speed, single data line theory can reach 25MB/s, 4-wire transfers can reach this 100M/s design a four line SD communications protocols.This design on the SD card agreement prepared by software: first in the SOPC Builder defines six I/O port: SD_CMD, SD_DAT0-DAT3, SD_CLK, which correspond to the SD card's command, data port, clock, and then in the NiosII IDE on the SD card transfer protocol writing C programs to six I/O port, in order to achieve the SD card's transport protocol.
Upon completion of the SD card data block read and write on the basis of the transplantations of file system FAT16, this does not affect the read-write speed conditions save FPGA resources.2.6 data transmission module design
In order to implement remote data interchange, this system uses the Ethernet network for data transmission.
Design uses DM9000A as Ethernet controller chip. DM9000A is DAVICOM company a high speed network controller with generic processor interfaces, one 10/100M PHY and 4K bytes SRAM. In order to achieve the network transmission of data, design needs to do things in a NiosII uClinux OS on transplantation, complete network underlying driver design, based on the network protocol of application development. One of the transplantations a NiosII on uClinux OS has been completed [4], the design of a critical task is complete the network driver design and application development.Based on the HAL device driver DM9000A design mainly consists of two steps: first the DM9000A Avalon bus interface logic design; secondly DM9000A read/write driver design; finally, in accordance with HAL driver mode will DM9000A driver transplantation into the HAL.
DM9000A as Avalon bus from peripherals to communicate with the NiosII. DM9000A of Avalon bus interface logic main complete chip signal and Avalon bus interface signal.DM9000A does not allow direct access to the chip internal registers, require a data port and index port to read and write.
Both ports by CMD pin control: when CMD received high level as data ports, CMD then low level to control port.Create a HAL device drivers including: creating a device instance and register devices [5].
Design for the structure of the LWIP defines a structure as DM9000A device alt_dev structure:Start the NiosII, alt_sys_init () on the device initialization, the initialization procedures are as follows:
Application design using TCP/IP, HTTP protocol, the Profiler as a Web server, the remote PC as client through a Web page displays the collected ECG waveform.
3 experimental results
System on the human body to the ECG signal acquisition, through the LCD panel displays in real time.
Through the SD card to store data, both Ethernet network to send data to a remote PC computers, the following are the system capabilities of validation and test results.3.1 signal conditioning module
ECG signal acquisition conditioning module is designed for the acquisition board, main measurement parameters for preamplifiers channel bandwidth, the zoom capability and notch characteristics.
After the test, a test signal in 1--the band bandwidth 1KHz enlarged gain basic stability in 12.1dB, that is, the channel bandwidth can ≥ 1kHz; In frequency is 20Hz and 50Hz, amplifier for 40--800mV signal amplification ability to gain and no obvious changes in the basic stability in 11.7 dB--13.1 dB; at the same time, notch filter for signal filtering, 50Hz will enlarge the gain control to 0.5 dB below. Therefore, based on the characteristics of the ECG in acquisition conditioning module can access the body of the stability of the ECG signal.3.2 signal display module
Figure 5 is a collection of ECG by local LCD panel display in real time.
The results from the display, ECG PQRST five characteristics of point clear, waveform smoothing, and actual measurement stability without interference, truly reflecting the acquisition of ECG.Figure 5 ECG display in local LCD Panel
3.3 network transmission module
In the design, realization of network interfaces so that the collected ECG via Ethernet is sent to the remote PC, remote transmission of data.
Under the TCP/IP Protocol and the HTTP protocol, signal processing through packaged and sent to the network. In the remote PC, through a Web browser can view the server-side collection to the ECG waveform. Figure 6 is an ECG on a remote PC side of the page displays the result on the browser. The test results display and LCD panel displays local waveforms are basically the same, enabling remote transmission function.Figure 6 shows the remote PC-side page
Experiments show that the ECG monitoring system in real time and accurate implementation of data acquisition, display, store and transport capabilities.
4 conclusions
Design incorporates SOPC technology and IP reuse, reduced system development cycle, while the system is portable, flexibility, features, extensible, and other functions.
Porting uClinux OS through, so that the system has a powerful network functions and a more robust system stability. But the design is adopted the system-level functionality to verify that no specific account of modern portable product power consumption, and so on, away from the real product is still some distance away.Reference documents:
[1] Glykas, Michael;
Chytas, Panagiotis. Next generation of methods and tools for team work based care in speech and language therapy: Telematics and Informatics, v 22, n 3, August, 2005, p 135-160.[2] Li LAN Ying .NiosII embedded soft core SOPC design principle and applications [M]-Astronautics .2006.
[3] TI.TLC549 DATASHEET[J].http://www.TI.com.
[4] Jiang Wei Springs; before the King; Wu Shu chuen. based on the study of uClinux NiosIl and application [J]. in science, technology and engineering, 2006.4 (6): 1069-1075
[5] ALTERA.NiosII Documentations[J]. http://www.altera.com.
[6] Glykas, Michael;
Chytas, Panagiotis. Next generation of methods and tools for team work based care in speech and language therapy: Telematics and Informatics, v 22, n 3, August, 2005, p 135-160.[7] Ogawa, Hidekuni;
Yonezawa, Yoshiharu; Maki, Hiromichi; Sato, Haruhiko; Caldwell, W. Morton A web-based home welfare and care services support system: Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings, v 3, 2002, p 1893.[8] Designing smart health care technology into the home of the future Warren, Steve (Sandia Natl Lab);
Craft, Richard L. Source: Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings, v 2, 1999, p677
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