Portable devices for critical power management circuit design

Due to the increasing integration of functions, as well as the overall dimensions of shrinking, the latest generation of rich smaller portable devices will enable power management design play a key role.

In General, portable devices including microprocessors, I/O peripherals, LED backlight, Flash memory and/or hard disk drive (HDD), digital and analog circuit, these function modules to power requirements. To enable these features module to work correctly and to minimize power consumption for longer battery life, system design engineers faced with how to design embedded power management solutions to meet the challenges of power requirements. This article on the power requirements are analysed, and focuses on how to design these power management circuit.

Power supply for microprocessors

Microprocessors are handling a variety of data and commands in core devices, most microprocessors used CMOS circuits with switch power consumption and power dissipation.

Digital circuit in every switch on the digital circuit output capacitor for charge and discharge and the resulting power expressed by the following formula:

Where c is the total load capacitance, the switching frequency fS, VCORE as applied to the power supply voltage microprocessor.

Under this formula was informed: clock frequency reduction will make power linear decrease, reduce the voltage of a quadratic equation can lead to a power-down. With microprocessor processing at an increasing rate, imposed on the microprocessor would reduce the voltage is less than 1V to minimize power consumption.

Microprocessor is the most common power supply voltage range 1.0 ~ 1.5V.

From voltage requirements, most microprocessors have strict voltage tolerance, in a stable condition and load transient voltage tolerance when not to 100mV. The microprocessor to low operating voltage and high current (with heavy edge slope), power management design engineers face must meet strict voltage transient requirements, but also to solve system power budgets and battery run time (high conversion efficiency). Microprocessor power consumption is usually the total system power consumption by 30-40%. Usually the portable device powered by lithium-ion battery, adopted LiCo02 cathode materials, their typical battery voltage range between 3.0 ~ 4.2V.

Figure 1 synchronous buck converter topology can effectively converts the battery voltage low core voltage.

Typically, with integrated MOSFET of fixed frequency pulse width modulation (PWM) DC/DC converter in normal load conditions have 90% conversion efficiency, but due to the switching losses and gate driver loss, their light load conditions (such as portable devices in standby mode) is less efficient. To enable a portable device for battery standby time converter in light load conditions provide high efficiency is important.

Figure 1: (a) synchronous buck converter topology map; (b) load transient process load current and inductor current

First of all is to design work in buck converters non-synchronous mode, thus not minimize and loop current related conduction loss caused by the negative inductor current.

In addition, pulse frequency modulation or pulse jump (pulse skip) mode is usually used to minimize a gate drive and switching losses. Development such as TI's power-saving mode, and other proprietary technology by closing the section control circuit to reduce the switching loss and PWM controller's static current minimum. 150 μ A load conditions, you can implement a low-18 μ A static electricity and more than 70% efficiency.

However, on a lighter load to high load transient run, this step-down converter introduces another challenge, that is, it needs a delay time to wake the PWM controller and put it into operation.

In this delay time, output capacitor must be load power supply, this would introduce a fixed frequency PWM converter for additional voltage drop. How to overcome the power save mode from the negative effects? microprocessor voltage specification allows a ± 5% of the total tolerance, including a steady state and transient errors and the load. You can set the light load output voltage increase 1% to compensate for delays due to control circuit wakes up additional pressure drop.

In fact, on mobile processors, increasing light load output voltage is the usual practice, this practice is known as a load line adjustment.

This technique increases the transient voltage swing, so it allows for additional voltage drop for compensation or the use of smaller output capacitor. In addition, the control loop design and inductance design on voltage transient response of very large. So, how do you choose the correct inductance and design control loop bandwidth to achieve fast transient response and in maintaining a high efficiency at the same time meet the voltage transient requirements?

From less than 1mA load to full load step load transient, voltage transient response shall normally be ±1% or less.

When the step load is applied to the system and output capacitance, voltage transient and equivalent series resistance (ESR) and convert the delay. Typically will use small ESR ceramic capacitors, therefore, the design by optimizing loops and inductance values to minimize the output capacitor voltage transient the ends of the most challenging. Output capacitor need in transient response during load current. Microprocessor is the slope of the required current than buck converters inductor current slope. Load current and inductor current difference between determines the need to provide the output capacitor charge amount, as Figure 1 (b) below. If you can reduce the charge of non-equilibrium, you can reduce the transient voltage, reduced output capacitor. Inductor current slope increases, the faster the transient response, the low pressure drop, transient response depends on the inductor current to follow the way of load currents. Inductor current rise time and described here is closely related to the control loop bandwidth.

Of these, fC for closed-loop

Loop bandwidth. On the other hand, feedback control loop in light to heavy load during the duty increase, resulting in a net in inductive voltage increases at both ends, this causes increased inductance-current. Average inductance current rise time obtained by the following formula:

Where Δ L, VIN, and D respectively inductors, input voltage and the duty cycle of added value.

Given the bandwidth to provide the same fast transient response of maximum inductance inductance is known as critical. The critical inductance inductance for optimized, in order to achieve maximum efficiency with as high bandwidth and low inductance-current ripple. Through the above two equations can be given a loop bandwidth to achieve the fastest transient response of critical inductance.

Where Δ D M A X to load transient period maximum duty cycle of added value.

This shows that a small inductor or you can get high loop bandwidth for fast load transient response to transient voltage requirements. Figure 2 gives a small inductor and large inductive output voltage transient response curve, it indicates that the inductive load smaller and faster transient response.