MB86S02 based on FPGA and digital image processing system design

0 introduction

Image processing technology is the information science in the last ten years the most rapidly developing one of the subjects.

At present, digital image processing technology has been widely used in aerospace, communications, medical and industrial production and other fields. However, if you simply use the ready-made dedicated video processing chip, it is virtually impossible to design the products with independent intellectual property rights. As the network technology, large scale integrated circuit, too (ASIC) and field-programmable gate array (FPGA), their images are increasingly widely in the field of application, at the same time, the image processing design also is moving fast, large capacity, small size, light weight, this is an image processing system design and implementation of new methods and ideas.

1 system features

The system diagram as shown in Figure 1, the chart shown in Figure 2.

It to embedded FPGA Nios, junior, senior, and image acquisition chip and memory, and other peripheral chip embedded into the system, thereby achieving image acquisition and processing, and display and processing of data by using a solution of words is through the PSTN network is sent to the receiver (monitoring center) to the monitoring center to use on a PC computer program written in processing the image displayed.

2 image processing of

21 image acquisition module

Image acquisition module using Fujitsu company produced a 375x293 (10 million) pixel (CIF KE-) CMOS image sensor MV86S02, the chip-chip integrated color signal processor.

This will be the color CMOS image sensor and signal processor are integrated into one chip technology can reduce system power consumption and size. Because MV86S02 contains image acquisition of all of the front-end processing capabilities, and can be directly output digital signals. Dramatically facilitate the user's use, simplified development work, while at the same time improves the performance of the system.

FPGA with MB86S02 type CMOS image module connected to through the VHDL program MB86S02 collected digital image data stored in the SRAM for subsequent LCD display and data processing, and then you can also use the UART module or RTL8019 module to have saved image data sent to the PC, the last in the PC of the receiving program control displays the received images.

Image acquisition module of sequential simulation results as shown in Figure 3.

2 2 image low-end processing module

Image of low-level processing of large volumes of data and hence require faster, but the algorithm is relatively simple.

This article in the FPGA in low-end processing of median filtering quick processing algorithms and hardware circuit, median filter window all pixel's degree of gray values are from small to large (or O, from largest to smallest) order, and the gray value series of intermediate values instead of window Center like cable point of gray values. This means that the implementation process to do a lot of comparison and assignment operations, improved quick filtering algorithm design idea is broken down into two dimensional filter array to a dimension. That is, first of all find out filter window horizontal lines pixel grayscale values in value, and then find out the level of the row values in a value as filtering the results. Figure 4 shows the quick median filtering sequential simulation figure.

2 3 advanced image processing and display

Advanced image processing can reference a low-level approach to implementation.

But the operation of the data volume is small, the algorithm relatively complex, which also has a serial sex. This example continues to use the hardware implementation, it is necessary to take up a lot of hardware resources, so that you can use embedded CPUs. Because CUu and FPGA architecture that has a lot of bandwidth, data exchange is also very convenient, therefore, this article is based on FPGA programmable system-on-chip (SOPC) technology, advanced image processing by N I o s Ⅱ core CPU with customized instruction and peripheral circuitry to achieve to improve processing speed,

The image shows the fork by embedding N I o s Ⅱ processor and VGA display controller.

3 closing

Inline Nios processor for core of FPGA, you can complete the image acquisition control, low-level, advanced image processing and image display design.

As a programmable FPGA-based system-on-chip (SOPC) technology and large-scale high-performance FPGA-rich resources. Therefore, the use of embedded N I o s Ⅱ processor and the necessary peripheral circuit, can make the image processing speed, power, flexibility, development cycles and cost control have been improved greatly.