FPGA-based digital image b-real-time data acquisition system

1 Introduction

The majority of medical ultrasound imaging technology using ultrasonic pulse echo method, namely, the use of ultrasonic probes have entered the body, the human reflection of echo through the transducer converts an electrical signal is received, after extraction, amplification, processing, and digital scan converter convert to standard video signal, and finally by the monitor to display.

FPGA + ARM based 9 hardware platform of digital ultrasound diagnostic instrument, a front-end probe returned echo signals required by real-time acquisition system for beamformer, related processing, collection and transport to ARM embedded signal processing systems, video, real-time data volume, therefore use FPGA + SRAM constitutes real-time acquisition system, the speed and capacity to meet the above requirements. Focus on b-imaging system for logic control for FPGA by video image acquisition theory and implementation.

2 system working principle

As shown in Figure 1, acquisition system first by DBF converter for multichannel ultrasonic echo signal beam synthesis, digital beam synthesizer on a different channel signal delay, make the same point signal phase, at the same time on multiple channels of echo signal space domain on Windows, a similar matching filter, you can improve the signal to noise ratio.

And then on the synthesis of the ultrasound signal after a frame related pretreatment, i.e. image frames and frames between the corresponding pixel grayscale on smoothing. Because the overlay on the image noise is related and has zero mean random noise, if in the same conditions to take the average of the number of frames instead of the original image, you can weaken the noise intensity. In the frame of the related process, FPGA to control data read, processing and storage. In order to meet the real-time video display, the data acquisition system with dual frame storage structure of ping-pong mechanism, FPGA read-write lock control. The frame-related processing after the turn of the video data is written to A frame to save and save the frame as frame B, read the controller according to the back-end processing speed reading frame data stored, sent to DMA controller, DMA controller opens DMA channels for data transmission. FPGA read/write control, in order to avoid while on a frame or to read and write, you need to set read-write mutex for storage status switch.

3 system design and implementation

3.1 DBF

For a 128 element and 32 transceiver channels ultrasonic probes, 32-channel AD conversion, it is divided into four groups, each group of 8-channel receiver channel, each group with a piece of FPGA, in the FPGA within first receive delay and dynamic focus then weighted sum, subsequent to a sum between group produces digital video signals in echocardiography.

Each group to the system diagram as shown in Figure 2:

On different channels of the echo signals for different delay is the key to achieving beam focus, delay the accuracy can be divided into coarse and fine delay delay: the delay is used to control the rough A/D sampling of start time, precision 32 ns, delay parameters by FPGA chip RAM read, replace the probe will be appropriate when the system controller writes the data to the RAM; fine-delay from sampling clock generator according to the different channels have different A/D sampling clock, clock phase, the mutual stagger the staggered value exactly equal to the array element propagation delay.

Considering that the system of real-time and detection of changes in depth, you need to use dynamic focusing. Dynamic focus is in A/D sampling begins, by reading the dynamic focusing parameter, in the sampling process control sampling clock generator.

Eight channels of echo signal a/d sampling, fed to the FPGA, the buffer to read into weighted after synchronization module, weighted modules from eight unsigned as digital multiplier.

Echo signal is multiplied by the respective weighting parameters after a dynamic focusing and weighted characters of data. 8 groups of data after 3-Adder get beam synthesis after ultrasonic digital video data.

3.2 frame related processing

Frames related modules as shown in Figure 3, the frame related controller and a piece of memory, the memory associated with the frame with a size of 256 kb SRAM (SRAM).

Frames related controller by FPGA, complete address, memory read/write control, frame-related calculation function, because real-time performance requirements that guarantee them to the rear-side double frame of data can not be broken, so taking into account the case-by-pixel data read and write at the same time the associated process, but also in the same pixel clock cycles to complete. Read and write to the controller within 1 pixel clock cycle in the first half of the need to read the data in memory and the current frame data related to processing; clock cycles of the second half of the related processing of data written to memory for later use, so rushed back-end data of double-frame remains and pixel clock corresponding continuous pixel data.

Frame-related workflow is as follows:

(1) address.

Address generation by a cable counter, input signal for frame synchronization signal CLK VS and pixel clock. Front-end for frame synchronization signal VS the counter reset signal, in the beginning of each frame, the counter is cleared to zero, then the pixel clock count generated address, CLK each pixel clock cycle address unchanged by this address memory read and write.

(2) reads the existing data and associated processing.

In a pixel clock cycle in the first half, CLK jump into a high level, reading and writing controller output read signal OEl as valid, read out the front frame in one pixel of data sent to the FPGA internal implementation in A outlet, Adder and arrive at the B-current frame of the corresponding pixel mean data together.

(3) data preservation and transmission.

In the same pixel clock cycle in the latter part, CLK jump into a low level, reading and writing controller output write signal WEl, related to finish processing the data is written back to the original address, at the same time the data is alsoSent to the frame to save and write the control module.

3.3 frames as table tennis, reading, writing and control mechanisms

Ultrasound video images need real-time acquisition and processing on the monitor, image storage must constantly writing data, and the need to continually read the data sent from storage back-end processing and display.

In addition, in order to meet this requirement, you can set the collection system for 2 sheet capacity as frames save, read and write through the ping-pong mechanism to manage, structure as shown in Figure 3. In order to ensure that any moment you can only have 1 piece frame as is write status, set 1 write mutex lock; at the same time, there can be only 1 piece frame as is read status, set a read a mutex. The system initially, 1 tablet frame as waiting for the write status, 1 tablet to wait for the read status; start, 2 blade is in read-write state turn conversion process, the process of conversion is the same, but the State phase 2 tablets, so that you can stagger the guarantee that the data can be continuously write and read frames. The mechanism as shown in Figure 4, the workflow is:

(1) acquisition process does not start, wait A frame to save into, obtain write write mutex; frames save b is waiting for read status, access to reading of the mutex;

(2) frame or write controller receives a signal, starting with the frame for the collection, starting at the judgment setting the frame as A write A valid signal WE2, frame as A begin writing the current frame data; at the same time frame as read controller settings frame as b read signal OE2_B effective, frames save B began to read the data;

(3) one end of frame, frame holds A write end, release write mutex; frames save b read over, release the read lock repulsion;

(4) wait for another frame, the frame as A mutual-exclusion lock for reading; frames save B get write lock read repulsion;

(5) another frame, write controller settings frame as B write signal WE2B effective, frames save B begin writing data; reading frame as A controller settings read signal OE2 A valid frame as A start to read out the data.

3.4 DMA transfers

On the whole ultrasound diagnostic instrument, the system to complete the video image data in real-time collection and the specified handle, high-performance ARM processor can handle up to millions of instructions per second, so the design of the data transfer is the key to improving system speed.

ARM treatment systems and external data can external memory via CPU access method implementations, but inefficient and does not meet the system requirements of real-time performance, and DMA data transfers to not consume CPU time and single-cycle throughput benefits for data transmission in real time video image acquisition systems in a wide range of applications. But because DMA transfer rate and front-end video image data input rate does not match, it is difficult to play out the advantages of DMA data transfers. Programmable FPGA control SRAM dual frame consisting of deposit is a good way to solve this problem; in addition, FPGA internal embedded a certain amount of RAM that can be configured to act as a buffer memory, the logical structure by Agile can be easily implemented on the input and output data flow control, become connection ARM treatment system and SRAM bonds and bridges.

4 closing

In the b-digital video image real-time acquisition system using FPGA as acquisition control part, first of all, you can improve system speed and system flexibility and adaptability: as in FPGA and ARM treatment systems using SRAM do data buffering and DMA transfers, greatly improving system performance; as a result of using FPGA programmable logic devices, ultrasonic for different video signal, as long as the FPGA logic to control a little modification, it may signal acquisition; FPGA peripheral hardware circuit is simple, so the hardware design, you can significantly reduce the complexity of hardware design.

The FPGA can be sequential logic debugging software simulation, thus lowering hardware debugging more difficult.